Location:
Search - vhdl spi
Search list
Description: SPI BUS VHDL实现-VHDL SPI BUS
Platform: |
Size: 853498 |
Author: davidluo |
Hits:
Description: VHDL 实现的SPI接口,在Altera EMP7128 上应用过-VHDL SPI interface, the application of Altera EMP off
Platform: |
Size: 889 |
Author: 陈同 |
Hits:
Description: 在FPGA下建立NiosII内核,并在该基础上设计SPI总线
Platform: |
Size: 13497390 |
Author: fengruozhuo |
Hits:
Description: SPI 接口的VHDL和Verilog实现。slave模式
Platform: |
Size: 4132 |
Author: szsz06@126.com |
Hits:
Description: ALTERA NIOS处理器,VHDL语言在QUARTUS编译通过,然后有C语言在NIOS SHELL下驱动,实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Platform: |
Size: 34816 |
Author: xf |
Hits:
Description: MMC卡的VHDL源代码实现,经过大批量生产验证-MMC card VHDL source code to achieve, through large-scale production test
Platform: |
Size: 5120 |
Author: 喻袁洲 |
Hits:
Description: 昨天在论坛上看到有人帖出了他写的并串转换VHDL代码,但是他自己说有问题,但是不知道怎么改。我大概看了一下,发现思路还是比较乱的。于是就写下了我自己的并串转换代码。-yesterday at the forum see someone points out his writing and string conversion VHDL code, But he said there are problems, but does not know how reform. I probably watched and found ideas is quite a mess. So I wrote on their own code and string conversion.
Platform: |
Size: 1024 |
Author: ZHAOBOO |
Hits:
Description: spi总线的vhdl代码,试了试可以用。希望能对开发者有所帮助。-spi bus vhdl code Shileshi can use. The hope is to help developers.
Platform: |
Size: 344064 |
Author: 李鸣 |
Hits:
Description: SPI串口的内核实现(vhdl),可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
Platform: |
Size: 13312 |
Author: efly |
Hits:
Description: freescale公司的SPI总线规范,非常详细,研究串行总线的朋友值得一看-Freescale
Platform: |
Size: 240640 |
Author: suzhenwei |
Hits:
Description: FPGA/CPLD VHDL语言实现SPI,拥有两种模式,FPGA/CPLD即可工作在主机模式,又可工作在从机模式 -FPGA/CPLD VHDL language SPI, have the two models, FPGA/CPLD can work in host mode, but also work in slave mode
Platform: |
Size: 248832 |
Author: 张焱 |
Hits:
Description: // This program accesses a SPI EEPROM using polled mode access. The F06x MCU
// is configured in 4-wire Single Master Mode, and the EEPROM is the only
// slave device connected to the SPI bus. The read/write operations are
// tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware
// connections of the F06x MCU are shown here:
Platform: |
Size: 72704 |
Author: 蓝天 |
Hits:
Description: 串行数据SPI master的开源控制器,verilog,内附说明-SPI master serial data open-source controller, verilog, containing a description
Platform: |
Size: 81920 |
Author: 王天 |
Hits:
Description: vhdl spi cpld fpga cofiguration
Platform: |
Size: 6144 |
Author: mohamad |
Hits:
Description: 经典spi IP 核心 FPGA是实现有说明文档-spi IP based on fpga
Platform: |
Size: 49152 |
Author: wuyou |
Hits:
Description: spi控制器,可以自己修改成8/16/32位模式-SPI controller
Platform: |
Size: 949248 |
Author: liangbo |
Hits:
Description: SPI接收模块,被注释掉的是发送模块,需要进一步地完善-SPI receiver module
Platform: |
Size: 1024 |
Author: qazmlp |
Hits:
Description: VHDL语言编写的SPI通信接口,可实现与单片机等外部MCU的通信,且只占用较少的引脚线-Written in VHDL SPI communication interface, can be realized with the microcontroller and other external MCU communication, and only takes less pin line
Platform: |
Size: 585728 |
Author: ldong1989 |
Hits:
Description: FPGA,VERILOG,SPI串口通信;(FPGA,VERILOG,SPI;;;;;;;;;)
Platform: |
Size: 2048 |
Author: dl121
|
Hits:
Description: VHDL spi ad9910 for FTW
Platform: |
Size: 2048 |
Author: Tienld2 |
Hits:
«
1
23
4
5
6
7
8
9
10
...
15
»